This invention relates to programmable logic integrated circuit devices, and more particularly to the organization of various types of resources (e.g., logic, memory, and interconnection conductors) on such devices.
It is known to provide programmable logic integrated circuit devices with blocks of programmable logic, blocks of memory (e.g., random access memory (“RAM”) or read-only memory (“ROM”)) that are accessible to the user, and programmable interconnection conductor resources for selectively conveying signals to, from, and between the logic and memory blocks (see, for example, Cliff et al. U.S. Pat. No. 5,550,782 and Cliff et al. U.S. Pat. No. 5,689,195, both of which are hereby incorporated by reference herein in their entireties). The logic blocks are programmable by the user to perform various logic functions desired by the user. The memory blocks may be used by the user to store and subsequently output data or to perform various logic functions desired by the user. The interconnection conductor resources are programmable by the user to make any of a wide range of connections between inputs of the device and inputs of the logic and memory blocks, between outputs of the logic and memory blocks and outputs of the device, and between outputs and inputs of the logic and memory blocks. Although each individual logic module (of which there may be several in each logic block) and memory block is typically able to perform only a relatively small logic or memory task, the interconnection conductor resources allow concatenation of these individual logic and memory tasks so that extremely complex functions can be performed if desired.
Improvements in integrated circuit fabrication technology are making it possible to make programmable logic devices with very large amounts of logic, memory, and interconnection conductor resources. Increasing the amounts of logic and memory on a programmable logic device has a tendency to call for more than a proportional increase in the amount of interconnection conductor resources provided. This is so because, at least in theory, it is desirable to be able to connect any inputs and outputs on the device to one another without other possibly desired connections being blocked or prevented. As the number of logic and memory blocks on the device increases, the number of inputs and outputs increases in approximately linear proportion. But the number of possibly desired connections between inputs and outputs tends to increase in a more exponential fashion. This can lead to excessive amounts of the total resources of the device being devoted to interconnection conductors and associated circuitry.
In view of the foregoing, it is an object of this invention to provide organizations for large programmable logic devices that help to reduce the need for excessive amounts of interconnection conductor resources on those devices.
It is a more particular object of this invention to provide arrangements for the logic and memory blocks on large programmable logic devices which facilitate provision of large amounts of anticipated interconnections on a “local” basis, using relatively short interconnection conductors, so that the amount of more “expensive” longer-length interconnection resources can be reduced, thereby helping to limit the fraction of overall device resources that must be devoted to interconnection resources.